TC1796中文资料英飞凌数据手册PDF规格书

Summary of Features

• High-performance 32-bit super-scalar TriCore V1.3 CPU with 4-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Single precision Floating Point Unit (FPU)

– 150 MHz operation at full temperature range

• 32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

• Multiple on-chip memories

– 2 Mbyte Program Flash Memory (PFLASH) with ECC

– 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation

– 136 Kbyte Data Memory (LDRAM, SRAM, SBRAM)

– 8 Kbyte Dual-Ported Memory (DPRAM)

– 48 Kbyte Code Scratchpad Memory (SPRAM)

– 16 Kbyte Instruction Cache (ICACHE)

– 16 Kbyte BootROM (BROM)

• 16-Channel DMA Controller

• 32-bit External Bus Interface Unit (EBU) with

– 75 dedicated address/data bus, clock, and control lines

– Synchronous burst Flash access capability

• Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2

• High performing on-chip bus structure

– Two 64-bit Local Memory Buses between EBU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– 32-bit Remote Peripheral Bus (RPB) for high-speed on-chip peripheral units

– Two bus bridges (LFI Bridge, DMA Controller)

• Peripheral Control Processor with single cycle instruction (PCP2)

– 16 Kbyte Parameter Memory (PRAM)

– 32 Kbyte Code Memory (CMEM)

• Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection

– Two High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction

– Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices

– Two High-Speed Micro Link interfaces (MLI) for serial inter-processor communication

– One MultiCAN Module with four CAN nodes and 128 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer (one CAN node supports TTCAN functionality)

– Two General Purpose Timer Array Modules (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

– Two 16-channel Analog-to-Digital Converter units (ADC) with selectable 8-bit, 10-bit, or 12-bit resolution

– One 4-channel Fast Analog-to-Digital Converter unit (FADC) with concatenated comb filters for hardware data reduction: supporting 10-bit resolution, min. conversion time of 280ns

• 44 analog input lines for ADC and FADC

• 123 digital general purpose I/O lines, 4 input lines

• Digital I/O ports with 3.3 V capability

• On-chip debug support for OCDS Level 1 and 2 (CPU, PCP3, DMA)

• Dedicated Emulation Device chip for multi-core debugging, tracing, and calibration via USB V1.1 interface available (TC1796ED)

• Power Management System

• Clock Generation Unit with PLL

• Core supply voltage of 1.5 V

• I/O voltage of 3.3 V

• Full automotive temperature range: -40° to +125°C

• P/PG-BGA-416-4 package