TC1767中文资料英飞凌数据手册PDF规格书

Introduction

This Data Sheet describes the Infineon TC1767, a 32-bit microcontroller DSP, based on the Infineon TriCore Architecture.

Summary of Features

• High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline

– Superior real-time performance

– Strong bit handling

– Fully integrated DSP capabilities

– Single precision Floating Point Unit (FPU)

– 133 MHz operation at full temperature range

• 32-bit Peripheral Control Processor with single cycle instruction (PCP2)

– 8 Kbyte Parameter Memory (PRAM)

– 16 Kbyte Code Memory (CMEM)

– 133 MHz operation at full temperature range

• Multiple on-chip memories

– 72 Kbyte Data Memory (LDRAM)

– 24 Kbyte Code Scratchpad Memory (SPRAM)

– 2 Mbyte Program Flash Memory (PFlash)

– 64 Kbyte Data Flash Memory (DFlash, represents 16 Kbyte EEPROM)

– Instruction Cache: up to 8 Kbyte (ICACHE, configurable)

– Data Cache: up to 4 Kbyte (DCACHE, configurable)

– 8 Kbyte Overlay Memory (OVRAM)

– 16 Kbyte BootROM (BROM)

• 8-Channel DMA Controller

• Sophisticated interrupt system with 2×255 hardware priorityarbitration levels serviced by CPU or PCP2

• High performing on-chip bus structure

– 64-bit Local Memory Buses between CPU, Flash and Data Memory

– 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units

– One bus bridge (LFI Bridge)

• Versatile On-chip Peripheral Units

– Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection

– Two High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction

– One serial Micro Second Bus interface (MSC) for serialport expansion to external power devices

– One High-Speed Micro Link interface (MLI) for serial inter-processor communication

– One MultiCAN Module with 2 CAN nodes and 64 free assignable message objects for high efficiency data handling via FIFO buffering and gateway data transfer

– One General Purpose Timer Array Modules (GPTA) with additional Local Timer Cell Array (LTCA2) providing a powerful set of digital signal filtering and timer functionality to realize autonomous and complex Input/Output management

• 32 analog inputlines for ADC

– 2 independent kernels (ADC0, ADC1)

– Analog supply voltage range from 3.3 V to 5 V (single supply)

– Performance for 12 bit resolution (@fADCI =10 MHz)

• 4 different FADC input channels

• Extreme fast conversion, 21 cycles of fFADC clock (262.5 ns @ fFADC = 80 MHz)

– 10-bit A/D conversion (higher resolution can be achieved by averaging of consecutive conversions in digital data reduction filter)

• 88 digital general purpose I/Olines (GPIO), 4 input lines

• Digital I/O ports with 3.3 V capability

• On-chip debug support for OCDS Level 1 (CPU, PCP, DMA, On Chip Bus)

• Dedicated Emulation Device chip available (TC1767ED)

– multi-core debugging, real time tracing, and calibration

– four/five wire JTAG(IEEE 1149.1) or two wire DAP (Device Access Port) interface

• Power Management System

• Clock Generation Unit with PLL

• Core supply voltage of 1.5 V

• I/O voltage of 3.3 V

• Full automotive temperature range: -40° to +125°C

• Package variant: PG-LQFP-176-5