SY89825U数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The SY89825U is a High Performance Bus Clock Driver with 22 differential LVPECL output pairs. This part is designed for use in low voltage (2.5V, 3.3V) applications which require a large number of outputs to drive precisely aligned, ultra low skew signals to their destination. The input is multiplexed from either LVDS or LVPECL by the CLK_SEL pin. The LVDS input includes a 100Ω internal termination, thus eliminating the need for external termination. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This eliminates any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control.The SY89825U features low pin-to-pin skew (35ps max.) --performance previously unachievable in a standard product having such a high number of outputs. The SY89825U is available in a single space saving package which provides a lower overall cost solution. In addition, a single chip solution improves timing budgets by eliminating the multiple device solution with their corresponding large part-to-part skew.

特性 Features

• LVPECL or LVDS input to 22 LVPECL outputs
• 100K ECL compatible outputs
• LVDS input includes 100Ω termination
• Guaranteed AC parameters over voltage:
• >2GHz fMAX (toggle)
• <35ps max. ch-ch skew
• Low voltage operation: 2.5V, 3.3V
• Temperature range: -40°C to +85°C
• Output enable pin
• Available in a 64-Pin EPAD-TQFP

简介

SY89825U属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的SY89825U时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。