SY89809AL数据手册集成电路（IC）的时钟缓冲器驱动器规格书PDF

描述 Description

The SY89809AL is a high-performance bus clock driver with nine differential High-Speed Transceiver Logic (HSTL) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications, which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state.This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control.The SY89809AL features low pin-to-pin skew (15ps typical) and low part-to-part skew (100ps typical). The SY89809AL is available in a single space-saving package, enabling a lower overall cost solution.

特性 Features

• 3.3V core supply, 1.8V output supply for reduced power
• LVPECL and HSTL inputs
• Nine differential HSTL (low-voltage swing) output pairs
• HSTL outputs drive 50Ω-to-ground with no offset voltage
• 750MHz maximum clock frequency
• Low part-to-part skew (100ps typical)
• Low pin-to-pin skew (15ps typical)
• Available in 32-pin TQFP

简介

SY89809AL属于集成电路（IC）的时钟缓冲器驱动器。由制造生产的SY89809AL时钟缓冲器，驱动器时钟缓冲器和驱动器集成电路产品族中的产品用于帮助信号在系统中传输，常用作频率/时间参考信号，以同步系统内的活动。尽管这些器件最常用到的功能就是缓冲（即，为使信号不受驱动负载的影响而从某个信号源复制信号），但是该产品族中的某些器件还能执行其他功能，例如选择性改变缓冲信号路径、按某个整数值分割信号频率，或进行所用电信号格式转换。