ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION

文件：194.12 Kbytes 页数：8 Pages

Micrel

麦瑞半导体

ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION

文件：194.12 Kbytes 页数：8 Pages

Micrel

麦瑞半导体

ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT

文件：172.95 Kbytes 页数：8 Pages

Micrel

麦瑞半导体

ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT

文件：172.95 Kbytes 页数：8 Pages

Micrel

麦瑞半导体

ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION

文件：194.12 Kbytes 页数：8 Pages

Micrel

麦瑞半导体

ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT AND OUTPUT TERMINATION

文件：194.12 Kbytes 页数：8 Pages

Micrel

麦瑞半导体

ULTRA-PRECISION CML DATA AND CLOCK SYNCHRONIZER W/ INTERNAL INPUT

文件：172.95 Kbytes 页数：8 Pages

Micrel

麦瑞半导体

Flip Flops, Logic Gates

The SY58051AU is an ultra-fast, low jitter universal logic gate with a guaranteed maximum data or clock throughput of 10.7Gbps or 8GHz, respectively. This AnyGate® differential logic device will produce many logic functions of two Boolean variables, such as AND, NAND, OR, NOR, DELAY, or NEGATION.The • Three matched-delay input pair provide any logic function: AND, NAND, OR, NOR\n• Guaranteed AC performance over temperature and voltage:\n• DC to >10.7Gbps data rate throughput\n• DC to >8GHz clock fMAX\n• <160ps Any In-to-Out tpd\n• 20ps typical tr / tf\n• Ultra low-jitter design:\n• 0.2psRMS typ;

Microchip

微芯科技

Backplane & Cable Management

The SY58052AU is an ultra-fast, precision, low jitter data- to-clock resynchronizer with a guaranteed maximum data throughput of 10.7Gbps and a maximum clock of 10.7GHz. The SY58052AU is an ideal solution for backplane retiming or retiming after the data passes through long trace lengths. Serial dat • Resynchronizes data to a reference clock\n• Guaranteed AC performance over temperature and voltage:\n• DC-to >10.7Gbps data rate throughput\n• DC-to >7GHz clock fMAX\n• <160ps Any In-to-Out tpd\n• 30ps typical rise/fall time\n• Ultra low-jitter design:\n• 0.3psRMS typical random jitter\n• 3psPP ty;

Microchip

微芯科技

ULTRA-PRECISION CML AnyGate WITH INTERNAL INPUT AND OUTPUT TERMINATION

Microchip

微芯科技