SY100S891JCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY100S891 is a 5-bit registered transceiver containing five bus transceivers with both transmit and receive registers. The bus outputs (BUS0 – BUS4) are specified for driving a 25 ohm bus and the receive outputs (Q0 – Q4) are specified for driving a 50 ohm line. The bus outputs have a normal high level output voltage and a normal low level output voltage when the bus enable (BUSEN0 – BUSEN4) is high. However, the output is switched to a cut-off level when a bus-enable is low.

FEATURES

■ 25Ω cut-off bus outputs

■ 50Ω receiver outputs

■ Transmit and receive registers with separate clocks

■ 1500ps max. delay from CLK1 to Bus Outputs (BUS)

■ 1500ps max. delay from CLK2 to Receiver Outputs (Q)

■ Individual bus enable pins

■ Internal 75KΩ input pull-down resistors

■ Voltage and temperature compensation for improved noise immunity

■ Industry standard 100K ECL levels

■ Extended supply voltage option:VEE = –4.2V to –5.5V

■ Available in 28-pin PLCC package