SY100S839VZCTR中文资料麦瑞半导体数据手册PDF规格书

DESCRIPTION

The SY100S839V is a low skew ÷2/4, ÷4/5/6 clock generation chip designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The device can be driven by either a differential or single-ended ECL/LVECL or, if positive power supplies are used, PECL/LVPECL input signal. In addition, by using the VBB output, a sinusoidal source can be AC-coupled into the device.

FEATURES

■ 3.3V and 5V power supply option

■ 50ps output-to-output skew

■ 50 duty cycle outputs

■ Synchronous enable/disable

■ Master Reset for synchronization

■ Internal 75KΩ input pull-down resistors

■ Available in 20-pin SOIC package