5V/3.3V 첨2, 첨4, 첨8 Clock Generation Chip

General Description The SY10/100EL34/L are low-skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low-skew clock generation applications. The internal dividers are synchronous to each other; therefore, the common output edges are all precisely aligned. The devices can be driven by eit

文件：176.55 Kbytes 页数：7 Pages

MICREL

麦瑞半导体

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：94.52 Kbytes 页数：3 Pages

ONSEMI

安森美半导体

첨2,첨4,첨8 Clock Generation Chip

Description The MC10/100EL34 is a low skew ÷2, ÷4, ÷8 clock generation chip designed explicitly for low skew clock generation applications. Features • 50 ps Output-to-Output Skew • Synchronous Enable/Disable • Master Reset for Synchronization • PECL Mode Operating Range: VCC = 4.2

文件：94.52 Kbytes 页数：3 Pages

ONSEMI

安森美半导体

5V/3.3V 첨2, 첨4, 첨8 CLOCK GENERATION CHIP

DESCRIPTION The SY10/100EL34/L are low skew ÷2, ÷4, ÷8 clock generation chips designed explicitly for low skew clock generation applications. The internal dividers are synchronous to each other, therefore, the common output edges are all precisely aligned. The devices can be driven by either a di

文件：57.33 Kbytes 页数：4 Pages

MICREL

麦瑞半导体