丝印：P9NK65Z；Package：TO-220；N-CHANNEL 650V - 1ohm - 7A TO-220/TO-220FP Zener-Protected SuperMESH?줡ower MOSFET

Description The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such ser

文件：158.63 Kbytes 页数：7 Pages

STMICROELECTRONICS

意法半导体

N-channel 650 V - 1 - 6.4 A TO-220 / TO-220FP

文件：351.35 Kbytes 页数：15 Pages

STMICROELECTRONICS

意法半导体

N-Channel 650V (D-S) Power MOSFET

文件：1.10916 Mbytes 页数：10 Pages

VBSEMI

微碧半导体

丝印：P9NK65ZFP；Package：TO-220FP；N-CHANNEL 650V - 1ohm - 7A TO-220/TO-220FP Zener-Protected SuperMESH?줡ower MOSFET

Description The SuperMESH™ series is obtained through an extreme optimization of ST’s well established strip-based PowerMESH™ layout. In addition to pushing on-resistance significantly down, special care is taken to ensure a very good dv/dt capability for the most demanding applications. Such ser

文件：158.63 Kbytes 页数：7 Pages

STMICROELECTRONICS

意法半导体

N-channel 650 V - 1 - 6.4 A TO-220 / TO-220FP

文件：351.35 Kbytes 页数：15 Pages

STMICROELECTRONICS

意法半导体

N-channel 650 V - 1 - 6.4 A TO-220 / TO-220FP

文件：351.35 Kbytes 页数：15 Pages

STMICROELECTRONICS

意法半导体

N沟道650 V - 1 Ohm - 6.4 A - TO-220有齐纳管保护的SuperMESH(TM) 功率MOSFET

These devices are N-channel Zener-protected Power MOSFETs developed using STMicroelectronics' SuperMESH™ technology, achieved through optimization of ST's well established strip-based PowerMESH™ layout. In addition to a significant reduction in on-resistance, this device is designed to ensure a high • 100% avalanche tested \n• Low input capacitance and gate charge \n• Low gate input resistance \n• Extremely high dv/dt and avalanche capabilities;

ST

意法半导体

N沟道650 V、1 Ohm、6.4 A TO-220FP有齐纳管保护的SuperMESH(TM) 功率MOSFET

These devices are N-channel Zener-protected Power MOSFETs developed using STMicroelectronics' SuperMESH™ technology, achieved through optimization of ST's well established strip-based PowerMESH™ layout. In addition to a significant reduction in on-resistance, this device is designed to ensure a high • 100% avalanche tested \n• Low input capacitance and gate charge \n• Low gate input resistance \n• Extremely high dv/dt and avalanche capabilities;

ST

意法半导体