STM32WBA50KG数据手册ST中文资料规格书

描述 Description

The STM32WBA50KG multiprotocol wireless and ultra-low power devices embed a powerful and ultra-low power radio compliant with the Bluetooth® SIG Low Energy specification 5.4. They operate at a frequency of up to 100 MHz.

The devices integrate a 2.4 GHz RADIO supporting Bluetooth Low Energy, and make possible to use proprietary protocols.

The STM32WBA50KG are based on a high-performance Arm Cortex-M33 32-bit RISC core, featuring a single-precision floating-point unit (FPU), supporting all the Arm single-precision data-processing instructions and all the data types. This core also implements a full set of DSP (digital signal processing) instructions and a memory protection unit (MPU) that enhances the application security.

The devices embed high-speed memories (1 Mbyte of flash memory and 64 Kbytes of SRAM), an extensive range of enhanced I/Os and peripherals connected to AHB and APB buses on the 32-bit multi-AHB bus matrix.

A flexible life cycle is managed thanks to multiple levels readout protection and debug unlock with password.

Several protection mechanisms are available for embedded flash memory and SRAM, namely readout and write protection.

The devices embed several peripherals reinforcing security: a fast AES coprocessor, a PKA (public key accelerator), a HASH hardware accelerator, and a true random number generator.

Active tamper detection and protection against transient perturbation attacks, is achieved thanks to several internal monitoring generating secret data erase in case of attack. This helps to fit the PCI requirements for point of sales applications.

Hardware semaphores enable the synchronization between software processes.

The devices offer one 12-bit ADC (2.5 Msps), a low-power RTC, one 32-bit general-purpose timer, one 16-bit PWM timer for motor control, one 16-bit general-purpose timer, and one 16-bit low-power timer. They also feature standard and advanced communication interfaces, namely one I2C, one SPI, one USART, and one low-power UART.

The STM32WBA50KG operate in the -40 to 85 °C (105 °C junction) temperature range from a 1.71 to 3.6 V power supply.

The design of low-power applications is enabled by a comprehensive set of power-saving modes.

Many peripherals (including radio, communication, analog, and timer peripherals) can be functional and autonomous in Stop mode with direct memory access thanks to BAM (background autonomous mode) support.

Some independent power supplies are supported, like an analog independent supply input for ADC, and radio dedicated supply inputs for the 2.4 GHz RADIO.

The STM32WBA50KG devices are available in an UFQFPN32 package.

特性 Features

• Includes ST state-of-the-art patented technology
• Ultra-low power radio
•2.4 GHz radio
•RF transceiver supporting Bluetooth® Low Energy specification 5.4
•RX sensitivity: -96 dBm (Bluetooth® Low Energy at 1 Mbps)
•Programmable output power, +4 dBm with 1 dB steps
•Integrated balun to reduce BOM
•Single crystal operation
•Suitable for systems requiring compliance with radio frequency regulations ETSI EN 300 328, EN 300 440, FCC CFR47 Part 15 and ARIB STD-T66
• Operating conditions:
•1.71 to 3.6 V power supply
•-40 to 85 °C temperature range
• Ultra-low power platform with FlexPowerControl
•Autonomous peripherals with DMA, functional down to Stop 1 mode
•160 nA Standby mode (8 wake-up pins)
•2.25 µA Standby mode with 16-Kbyte SRAM
•20.2 µA Stop mode with 16-Kbyte SRAM
•41.8 µA/MHz Run mode at 3.3 V
•Radio: Rx 7.91 mA / Tx at 0 dBm 10.51 mA
•Embedded regulator LDO
• Core: Arm® 32-bit Cortex®-M33 CPU with MPU, DSP, and FPU
• ART Accelerator: 8-Kbyte instruction cache allowing 0-wait-state execution from flash memory (frequency up to 100 MHz, 150 DMIPS)
• Benchmarks
•1.5 DMIPS/MHz (Drystone 2.1)
•410 CoreMark® (4.10 CoreMark/MHz)
• Real time clock (RTC) with hardware calendar, alarms, and calibration
• Clock sources
•32 MHz crystal oscillator
•32 kHz crystal oscillator (LSE)
•Internal low-power 32 kHz (±5%) RC
•Internal 16 MHz factory trimmed RC (±1%)
•PLL for system clock and ADC
• 存储器
•1 Mbyte flash memory with ECC, including 256 Kbytes with 100k cycles
•64-Kbyte SRAM, including 48 KB with parity check
•512-byte (32 rows) OTP
• Rich analog peripherals (independent supply)
•12-bit ADC 2.5 Msps, with hardware oversampling
• Communication peripherals
•Two UARTs (ISO 7816, IrDA, modem)
•SPI
•I2C Fm+ (1 Mbit/s), SMBus/PMBus®
• System peripherals
•Touch sensing controller, up to 12 sensors, supporting touch key, linear, and rotary touch sensors
•One 16-bit, advanced motor control timer
•One 16-bit timer
•One 32-bit timer
•One low-power 16-bit timer (available in Stop mode)
•One Systick timer
•Two watchdogs
•8-channel DMA controller, functional in Stop mode
• Security and cryptography
•Flexible life cycle scheme with RDP and password protected debug
•AES co-processor
•Public key accelerator
•HASH hardware accelerator
•True random number generator, NIST SP800-90B compliant
•96-bit unique ID
•Active tampers
•CRC calculation unit
• General purpose input/output:
•20 I/Os (most of them 5 V-tolerant) with interrupt capability
• Development support
•Serial wire debug (SWD), JTAG
• ECOPACK2 compliant packages