MPU with Dual Arm Cortex-A35 @1.5GHz, Cortex-M33 @400MHz, 3xEthernet (2+1 switch), 3xFD-CAN, LVDS/DSI, H.264, 3D GPU, AI/NN, Secure Boot, Cryptography, DRAM enc/dec, PKA

STM32MP25xC/F devices are based on the high-performance single or dual-core Arm® Cortex®-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex®‑A35 • Includes ST state-of-the-art patented technology. \n• Cores \n •Up to 64-bit dual-core Arm® Cortex®-A35• Up to 1.5 GHz\n• 32-Kbyte I + 32-Kbyte D level 1 cache for each core\n• 512-Kbyte unified level 2 cache\n• Arm® NEON™ and Arm® TrustZone® \n \n •32-bit Arm® Cortex®-M33 with FPU/MPU• Up to 400 ;

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