Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Evaluation board with STM32MP257F MPU

Features • STM32MP257FAI3 microprocessor based on the Arm® dual‑core Cortex®‑A35 1.5 GHz and Cortex®‑M33 400 MHz in a TFBGA436 package • ST power management STPMIC25 • Two 16‑Gbit DDR4 DRAMs • 512-Mbit S‑NOR flash memory • 32-Gbit eMMC v5.0 • Three 1‑Gbit/s Ethernet (RGMII) with TSN switch

文件：873.08 Kbytes 页数：7 Pages

STMICROELECTRONICS

意法半导体