Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

Arm® based dual Cortex®-A35 1.5 GHz Cortex®-M33 MPU, AI, 3D GPU, video encoder/decoder, TFT/DSI/LVDS, USB 3.0, PCIe®, crypto

Features Includes ST state-of-the-art patented technology. Cores • Up to 64-bit dual-core Arm® Cortex®-A35 – Up to 1.5 GHz – 32-Kbyte I + 32-Kbyte D level 1 cache for each core – 512-Kbyte unified level 2 cache – Arm® NEON™ and Arm® TrustZone® • 32-bit Arm® Cortex®-M33 with FPU/MPU – Up t

文件：16.63568 Mbytes 页数：241 Pages

STMICROELECTRONICS

意法半导体

MPU with Dual Arm Cortex-A35 @1.5GHz, Cortex-M33 @400MHz, 2xEthernet, 3xFD-CAN, Secure Boot, Cryptography, DRAM enc/dec, PKA

STM32MP25xC/F devices are based on the high-performance single or dual-core Arm® Cortex®-A35 64-bit RISC core operating at up to 1.5 GHz. The Cortex®‑A35 processor includes a 32-Kbyte L1 instruction cache for each CPU, a 32-Kbyte L1 data cache for each CPU, and a 512-Kbyte L2 cache. The Cortex®‑A35 • Includes ST state-of-the-art patented technology. \n•Up to 64-bit dual-core Arm® Cortex®-A35• Up to 1.5 GHz\n• 512-Kbyte unified level 2 cache\n•32-bit Arm® Cortex®-M33 with FPU/MPU• Up to 400 MHz \n• Arm® TrustZone®\n•32-bit Arm® Cortex®-M0+ in SmartRun domain• Up to 200 MHz (up to 16 MHz in auto;

ST

意法半导体