主流高性能系列，Arm Cortex-M3 MCU，具有64 KB Flash存储器，72MHz CPU，电机控制，USB和CAN

STM32F103xx中等容量高性能系列，集成了工作频率为72 MHz的高性能Arm® Cortex®-M3 32位RISC内核、高速嵌入式存储器(高达128KB的Flash存储器和20KB的SRAM存储器)，以及大量连接至2条APB总线的增强型I/O与外设。所有器件均提供2个12位ADC、3个16位通用定时器、2个PWM定时器以及标准和高级通信接口：多达2个I2C和SPI、3个USART、1个USB和1个CAN。\n\n 器件的工作电压为2.0 V到3.6 V。工作温度范围为-40到+85 °C，可扩展至-40到+105 °C。这些器件均提供一组全面的节能模式，支持用户实现低功耗应用设计。\ • Arm®32位Cortex®-M3 CPU内核 \n •最大频率72 MHz，以零等待周期访问存储器时的性能达1.25 DMIPS/MHz (Dhrystone 2.1) \n •单周期乘法和硬件除法指令 \n• 存储器 \n •64到128 KB Flash \n •20 KB SRAM \n• 时钟、复位和电源管理 \n •2.0 V到3.6 V应用电源和I/O \n •上电复位 (POR)、掉电复位 (PDR) 和可编程电压检测器 (PVD) \n •4至16 MHz晶振 \n •内置经工厂调校的8 MHz RC振荡器 \n •内置40 kHz RC振荡器 \n •用于CPU时钟的P;

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意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Medium-density performance line Arm®-based 32-bit MCU with 64 or 128 KB Flash, USB, CAN, 7 timers, 2 ADCs, 9 com. interfaces

Features  Arm® 32-bit Cortex®-M3 CPU core – 72 MHz maximum frequency, 1.25 DMIPS / MHz (Dhrystone 2.1) performance at 0 wait state memory access – Single-cycle multiplication and hardware division  Memories – 64 or 128 Kbytes of Flash memory – 20 Kbytes of SRAM  Clock, reset and sup

文件：2.03321 Mbytes 页数：116 Pages

STMICROELECTRONICS

意法半导体

Performance line, ARM-based 32-bit MCU with Flash, USB, CAN, seven 16-bit timers, two ADCs and nine communication interfaces

Features ■ Core: ARM 32-bit Cortex™-M3 CPU – 72 MHz, 90 DMIPS with 1.25 DMIPS/MHz – Single-cycle multiplication and hardware division – Nested interrupt controller with 43 maskable interrupt channels – Interrupt processing (down to 6 CPU cycles) with tail chaining ■ Memories –

文件：1.08161 Mbytes 页数：67 Pages

STMICROELECTRONICS

意法半导体