1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

文件：154.05 Kbytes 页数：29 Pages

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PHI

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

文件：248.05 Kbytes 页数：30 Pages

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

文件：154.05 Kbytes 页数：29 Pages

PHI

PHI

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

文件：248.05 Kbytes 页数：30 Pages

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

文件：154.05 Kbytes 页数：29 Pages

PHI

PHI

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

文件：248.05 Kbytes 页数：30 Pages

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

文件：248.05 Kbytes 页数：30 Pages

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

文件：154.05 Kbytes 页数：29 Pages

PHI

PHI

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications

Overview Archived content is no longer updated and is made available for historical reference only.\n The SSTUB32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. The register is configurable (using configuration pins C0 a \n•Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications\n•Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode\n•Controlled output impedance drivers enable optimal signal integrity and speed\n•Meets or exceeds SSTUB32866 JEDEC standard speed performance\n•Supports up t;

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