首页 >SSTUB32868>规格书列表
| 零件编号 | 下载 订购 | 功能描述/丝印 | 制造商 上传企业 | LOGO |
|---|---|---|---|---|
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2CONFIDENTIAL Features •28-bit1:2registeredbufferwithparitycheckfunctionality •SupportsSSTL_18JEDECspecificationondatainputs andoutputs •SupportsLVCMOSswitchinglevelsonCSGENand RESETinputs •Lowvoltageoperation:VDD=1.7Vto1.9V •Availablein176-ballLFBGApackage | RENESASRenesas Technology Corp 瑞萨瑞萨科技有限公司 | RENESAS | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2CONFIDENTIAL Features •28-bit1:2registeredbufferwithparitycheckfunctionality •SupportsSSTL_18JEDECspecificationondatainputs andoutputs •SupportsLVCMOSswitchinglevelsonCSGENand RESETinputs •Lowvoltageoperation:VDD=1.7Vto1.9V •Availablein176-ballLFBGApackage | RENESASRenesas Technology Corp 瑞萨瑞萨科技有限公司 | RENESAS | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Features •28-bit1:2registeredbufferwithparitycheckfunctionality •SupportsSSTL_18JEDECspecificationondatainputs andoutputs •SupportsLVCMOSswitchinglevelsonCSGENand RESETinputs •Lowvoltageoperation:VDD=1.7Vto1.9V •Availablein176-ballLFBGApackage | RENESASRenesas Technology Corp 瑞萨瑞萨科技有限公司 | RENESAS | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Features •28-bit1:2registeredbufferwithparitycheckfunctionality •SupportsSSTL_18JEDECspecificationondatainputs andoutputs •SupportsLVCMOSswitchinglevelsonCSGENand RESETinputs •Lowvoltageoperation:VDD=1.7Vto1.9V •Availablein176-ballLFBGApackage | RENESASRenesas Technology Corp 瑞萨瑞萨科技有限公司 | RENESAS | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT | ||
28-BITCONFIGURABLEREGISTEREDBUFFERFORDDR2 Description This28-bit1:2configurableregisteredbufferisdesignedfor1.7Vto1.9VVDDoperation.AllinputsarecompatiblewiththeJEDECstandardforSSTL_18,exceptthechip-selectgate-enable(CSGEN),control(C),andreset(RESET)inputs,whichareLVCMOS.Alloutputsareedge-controlle | IDT Integrated Device Technology, Inc. | IDT |
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