1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

文件：143.78 Kbytes 页数：27 Pages

PHI

PHI

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

文件：161.5 Kbytes 页数：28 Pages

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

文件：161.5 Kbytes 页数：28 Pages

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

文件：143.78 Kbytes 页数：27 Pages

PHI

PHI

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

文件：161.5 Kbytes 页数：28 Pages

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

文件：143.78 Kbytes 页数：27 Pages

PHI

PHI

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

文件：161.5 Kbytes 页数：28 Pages

恩XP

1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-667 RDIMM applications

OverviewThe SSTUA32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC standard for the SSTUA32866 registered buffer. The register is configurable (using configuration pins C0 and C \n\n•Configurable register supporting DDR2 up to 667 MT/s Registered DIMM applications\n\n•Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode\n\n•Controlled output impedance drivers enable optimal signal integrity and speed\n\n•Exceeds JESD82-7 speed performance (1.8 ns max. single-bit switching;

恩XP

IC REGIST BUFFER 25BIT DDR 96BGA

Renesas

瑞萨