SPC5643AF0MLU2中文资料NXP 32-bit MCU, Power Arch core, 3MB Flash, 120MHz, -40/+125degC, Automotive Grade, QFP 176数据手册恩XP规格书

描述 Description

The MPC564xA family of MCUs offers enhanced powertrain functionality and addresses the harsh environments of mid-range gasoline and direct injection engines, advanced transmissions, and industrial applications.
Designed to help lower overall system costs
Offers higher performance than single-issue cores at the same frequency
Operates at low power for high-temperature environments, such as transmissions
Enables precision tuning to optimize fuel economy and reduce emissions
Improves shift control

特性 Features

• Up to 150 MHz Power Architecture® core with up to two instructions per cycle
• Up to 4 MB of on-chip flash memory with error correcting codes (ECC) and read while write (RWW) options
• Up to 192 KB on-chip RAM with standby functionality (32 KB) and ECC
• 8 KB instruction cache (with line locking), configurable as two- or four-way
• 3× eSCI, 3× DSPI with microsecond bus support and a reaction module
• 3× FlexCAN with 64 messages buffers, 1× FlexRayTM module (v2.1)
• 32-channel eTPU2 (second generation eTPU) and 24 unified eMIOS channels
• Up to 40 channels ADC (Dual ADC) with 670 ns conversion time
• 5-volt single supply with external ballast with multiple external supply: 5V, 3.3V and 1.2V
• Power reduction modes: slow, stop and stand-by modes

• This product is included in NXP®.s product longevity program, with assured supply for a minimum of 15 years after launch
• Ultra-Reliable MCUs