SN75LVDS86ADGG集成电路（IC）的驱动器接收器收发器规格书PDF中文资料

SN75LVDS86ADGG属于集成电路（IC）的驱动器接收器收发器。由德州仪器制造生产的SN75LVDS86ADGG驱动器，接收器，收发器该系列产品的主要功能是提供必需的硬件资源，以通过延长电缆或印制线进行通信。确切的功能会因所采用的通信协议而异，可能包括诸如瞬态抑制之类的功能，这些功能对于通信用途可能并非绝对必要，但对于可能的使用环境却是明智之选。

3:21 Data Channel Expansion at up to

178.5 Mbytes/s Throughput

Suited for SVGA, XGA, or SXGA Display

Data Transmission From Controller to

Display With Very Low EMI

Three Data Channels and Clock

Low-Voltage Differential Channels In and

21 Data and Clock Low-Voltage TTL

Channels Out

Operates From a Single 3.3-V Supply

Tolerates 4-kV HBM ESD

Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal

Pitch

Consumes Less Than 1 mW When Disabled

Wide Phase-Lock Input Frequency Range

of 31 MHz to 68 MHz

No External Components Required for PLL

Inputs Meet or Exceed the Standard

Requirements of ANSI EIA/TIA-644

Standard

Improved Replacement for the DS90C364

and SN75LVDS86

Improved Jitter Tolerance

See SN65LVDS86A-Q1 Data Sheet for

Information About the Automotive

Qualified Version

description

The SN65LVDS86A/SN75LVDS86A FlatLink receiver contains three serial-in 7-bit parallel-out shift registers

and four low-voltage differential signaling (LVDS) line receivers in a single integrated circuit. These functions

allow receipt of synchronous data from a compatible transmitter, such as the SN75LVDS81, ’83, ’84, or ’85, over

four balanced-pair conductors and expansion to 21 bits of single-ended low-voltage LVTTL synchronous data

at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at seven times the LVDS input

clock (CLKIN) rate. The data is then unloaded to a 21-bit-wide LVTTL parallel bus at the CLKIN rate. The

’LVDS86A presents valid data on the falling edge of the output clock (CLKOUT).

The ’LVDS86A requires only four line-termination resistors for the differential inputs and little or no control. The

data bus appears the same at the input to the transmitter and output of the receiver with the data transmission

transparent to the user(s). The only user intervention is the possible use of the shutdown/clear (SHTDN)

active-low input to inhibit the clock and shut off the LVDS receivers for lower power consumption. A low level

on this signal clears all internal registers to a low level.

The SN75LVDS86A is characterized for operation over ambient free-air temperatures of 0C to 70C. The

SN65LVDS86A is characterized for operation over the full Automotive temperature range of −40°C to 125°C.