SN75LVDS84DGG.B中文资料德州仪器数据手册PDF规格书

1FEATURES

23· 21:3 Data Channel Compression at up to 163

Million Bytes per Second Throughput

· Suited for SVGA, XGA, or SXGA Data

Transmission From Controller to Display With

Very Low EMI

· 21 Data Channels Plus Clock-In Low-Voltage

TTL and 3 Data Channels Plus Clock-Out

Low-Voltage Differential

· Operates From a Single 3.3-V Supply and

250 mW (Typ)

· 5-V Tolerant Data Inputs

· ESD Protection Exceeds 6 kV

· SN75LVDS84 Has Falling-Clock

Edge-Triggered Inputs

· Packaged in Thin Shrink Small-Outline

Package (TSSOP) With 20-Mil Terminal Pitch

· Consumes Less Than 1 mW When Disabled

· Wide Phase-Lock Input Frequency Range:

– 31 MHz to 68 MHz

· No External Components Required for PLL

· Outputs Meet or Exceed the Requirements of

ANSI EIA/TIA-644 Standard

· Improved Replacement for the DS90C561

DESCRIPTION

The SN75LVDS84 FlatLink™ transmitter contains three 7-bit parallel-load serial-out shift registers, a 7´ clock

synthesizer, and four low-voltage differential signaling (LVDS) line drivers in a single integrated circuit. These

functions allow 21 bits of single-ended low-voltage TTL (LVTTL) data to be synchronously transmitted over three

balanced-pair conductors for receipt by a compatible receiver, such as the SN75LVDS82 or SN75LVDS86.

When transmitting, data bits D0–D20 are each loaded into registers of the SN75LVDS84 on the falling edge of

the input clock signal (CLKIN). The frequency of CLKIN is multiplied seven times and then used to unload the

data registers in 7-bit slices and serially. The three serial streams and a phase-locked clock (CLKOUT) are then

output to LVDS output drivers. The frequency of CLKOUT is the same as the input clock, CLKIN.