SN74LVT543数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

These octal transceivers are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.
The 'LVT543 contain two sets of D-type latches for temporary storage of data flowing in either direction. Separate latch-enable (or) and output-enable(or) inputs are provided for each register to permit independent control in either direction of data flow.
The A-to-B enable () input must be low in order to enter data from A or to output data from B. Ifis low andis low, the A-to-B latches are transparent; a subsequent low-to-high transition ofputs the A latches in the storage mode. Withandboth low, the 3-state B outputs are active and reflect the data present at the output of the A latches. Data flow from B to A is similar but requires using the ,, andinputs.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
To ensure the high-impedance state during power up or power down,should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The SN74LVT543 is available in TI's shrink small-outline package (DB), which provides the same I/O pin count and functionality of standard small-outline packages in less than half the printed-circuit-board area.
The SN54LVT543 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT543 is characterized for operation from -40°C to 85°C.
 

特性 Features

• State-of-the-Art Advanced BiCMOS Technology (ABT) Design for3.3-V Operation and Low Static Power Dissipation
• Support Mixed-Mode Signal Operation (5-V Input and OutputVoltages With 3.3-V VCC)
• Support Unregulated Battery Operation Down to 2.7 V
• Typical VOLP (Output Ground Bounce)CC = 3.3 V, TA = 25°C
• ESD Protection Exceeds 2000 V Per MIL-STD-883C, Method 3015;Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17
• Bus-Hold Data Inputs Eliminate the Need for External PullupResistors
• Support Live Insertion
• Package Options Include Plastic Small-Outline (DW), ShrinkSmall-Outline (DB), and Thin Shrink Small-Outline (PW) Packages,Ceramic Chip Carriers (FK), and Ceramic (JT) DIPs