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SN74LVT18512数据手册集成电路(IC)的通用总线功能规格书PDF

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厂商型号

SN74LVT18512

参数属性

SN74LVT18512 封装/外壳为64-TFSOP(0.240",6.10mm 宽);包装为管件;类别为集成电路(IC)的通用总线功能;产品描述:IC SCAN TEST UNIV TXRX 64TSSOP

功能描述

具有 18 位通用总线收发器的 3.3V ABT 扫描测试设备

封装外壳

64-TFSOP(0.240",6.10mm 宽)

制造商

TI Texas Instruments

中文名称

德州仪器 美国德州仪器公司

原厂标识
数据手册

下载地址下载地址二

更新时间

2025-8-5 23:01:00

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SN74LVT18512规格书详情

描述 Description

The 'LVT18512 and 'LVT182512 scan test devices with 18-bit universal bus transceivers are members of the Texas Instruments SCOPETM testability integrated-circuit family. This family of devices supports IEEE Std 1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test circuitry is accomplished via the 4-wire test access port (TAP) interface. Additionally, these devices are designed specifically for low-voltage (3.3-V) VCC operation, but with the capability to provide a TTL interface to a 5-V system environment.In the normal mode, these devices are 18-bit universal bus transceivers that combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, or clocked modes. They can be used either as two 9-bit transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP in the normal mode does not affect the functional operation of the SCOPETM universal bus transceivers. Data flow in each direction is controlled by output-enable (OEAB\\ and OEBA\\), latch-enable (LEAB and LEBA), and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the devices operate in the transparent mode when LEAB is high. When LEAB is low, the A data is latched while CLKAB is held at a static low or high logic level. Otherwise, if LEAB is low, A data is stored on a low-to-high transition of CLKAB. When OEAB\\ is low, the B outputs are active. When OEAB\\ is high, the B outputs are in the high-impedance state. B-to-A data flow is similar to A-to-B data flow but uses the OEBA\\, LEBA, and CLKBA inputs. In the test mode, the normal operation of the SCOPETM universal bus transceivers is inhibited, and the test circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry performs boundary-scan test operations according to the protocol described in IEEE Std 1149.1-1990. Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI), test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface. The B-port outputs of 'LVT182512, which are designed to source or sink up to 12 mA, include equivalent 25-series resistors to reduce overshoot and undershoot. The SN54LVT18512 and SN54LVT182512 are characterized for operation over the full military temperature range of -55°C to 125°C. The SN74LVT18512 and SN74LVT182512 are characterized for operation from -40°C to 85°C.

特性 Features

• Members of the Texas InstrumentsSCOPETM Family of Testability Products
• Members of the Texas InstrumentsWidebusTM Family
• State-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC)
• Support Unregulated Battery Operation Down to 2.7 V
• UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• B-Port Outputs of 'LVT182512 Devices Have Equivalent 25-Series Resistors, So No External Resistors Are Required
• Compatible With the IEEE Std 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture
• SCOPETM Instruction Set
• IEEE Std 1149.1-1990 Required Instructions and Optional CLAMP and HIGHZ
• Parallel-Signature Analysis at Inputs
• Pseudo-Random Pattern Generation From Outputs
• Sample Inputs/Toggle Outputs
• Binary Count From Outputs
• Device Identification
• Even-Parity Opcodes
• Package Options Include 64-Pin Plastic Thin Shrink Small Outline (DGG) and 64-Pin Ceramic Dual Flat (HKC) Packages Using 0.5-mm Center-to-Center Spacings SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.

技术参数

  • 制造商编号

    :SN74LVT18512

  • 生产厂家

    :TI

  • VCC(Min)(V)

    :2.7

  • VCC(Max)(V)

    :3.6

  • Bits(#)

    :18

  • Voltage(Nom)(V)

    :3.3

  • F @ nom voltage(Max)(MHz)

    :160

  • ICC @ nom voltage(Max)(mA)

    :24

  • tpd @ nom Voltage(Max)(ns)

    :4.9

  • IOL(Max)(mA)

    :64

  • IOH(Max)(mA)

    :-32

  • Operating temperature range(C)

    :-40 to 85

  • Package Group

    :TSSOP | 64

供应商 型号 品牌 批号 封装 库存 备注 价格
TI/德州仪器
24+
NA/
251
优势代理渠道,原装正品,可全系列订货开增值税票
询价
TI(德州仪器)
24+
TSSOP646.1mm
7350
现货供应,当天可交货!免费送样,原厂技术支持!!!
询价
TI
20+
NA
53650
TI原装主营-可开原型号增税票
询价
TI/德州仪器
24+
TSSOP64
880000
明嘉莱只做原装正品现货
询价
TI
21+
TSSOP64
1709
询价
TI
16+
TSSOP
10000
原装正品
询价
TI/德州仪器
23+
TSSOP-64
5000
只有原装,欢迎来电咨询!
询价
TI/德州仪器
22+
TSSOP64
20000
原装现货,实单支持
询价
TI/德州仪器
25+
原厂封装
10280
原厂授权代理,专注军工、汽车、医疗、工业、新能源!
询价
TI
25+
TSSOP64
4500
全新原装、诚信经营、公司现货销售!
询价