SN74LV8T596_V01中文资料德州仪器数据手册PDF规格书

1 Features

• Latching logic with known power-up state provides

consistent start-up behavior

• Wide operating range of 1.65V to 5.5V

• 5.5V tolerant input pins

• LVxT enhanced inputs combined with open-drain

outputs provide maximum voltage translation

flexibility:

– Over 6.67Mbps operation, (RPU = 1kΩ,

CL = 30pF)

– Up translation from 1.2V to 5V with 1.8V supply

– Down translation from 5V to 0.8V or even less

with any valid supply

• Supports standard function pinout

• Latch-up performance exceeds 250mA

per JESD 17

2 Applications

• Digital signage

• Controlling an indicator LED

• Increase the number of outputs on a

microcontroller

3 Description

The SN74LV8T596 device contains an 8-bit, serial-in,

parallel-out shift register that feeds an 8-bit D-type

storage register. All inputs include Schmitt-triggers,

eliminating any erroneous data outputs due to slowedged

or noisy input signals. The storage register

has parallel open-drain outputs. Separate clocks are

provided for both the shift and storage register. The

shift register has a direct overriding clear (SRCLR)

input, serial (SER) input, and a serial output (QH')

for cascading. When the output-enable (OE) input is

high, the outputs are in a high impedance state. The

operation of the OE input does not impact the internal

register data

The input is designed with a reduced threshold circuit

to support up translation when the supply voltage

is larger than the input voltage. Additionally, the 5V

tolerant input pins enable down translation when the

input voltage is larger than the supply voltage. The

output level is always referenced to the supply voltage

(VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS

levels.