SN74LV8T595-Q1中文资料德州仪器数据手册PDF规格书

1 Features

• Latching logic with known power-up state provides

consistent start-up behavior

• Wide operating range of 1.65V to 5.5V

• 5.5V tolerant input pins

• Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

• 1.2V to 1.8V

• 1.5V to 2.5V

• 1.8V to 3.3V

• 3.3V to 5.0V

– Down translation:

• 5.0V, 3.3V, 2.5V to 1.8V

• 5.0V, 3.3V to 2.5V

• 5.0V to 3.3V

• Up to 150Mbps with 5V or 3.3V VCC

• Supports standard function pinout

• Latch-up performance exceeds 250mA

per JESD 17

2 Applications

• Digital signage

• Controlling an indicator LED

• Increase the number of outputs on a

microcontroller

3 Description

The SN74LV8T595 device contains an 8-bit, serial-in,

parallel-out shift register that feeds an 8-bit D-type

storage register. The storage register has parallel

3-state outputs. Separate clocks are provided for

both the shift and storage register. The shift register

has a direct overriding clear (SRCLR) input, serial

(SER) input, and a serial output (QH') for cascading.

When the output-enable (OE) input is high, the

storage register outputs are in a high-impedance

state. Internal register data and serial output (QH') are

not impacted by the operation of the OE input.

The input is designed with a reduced threshold circuit

to support up translation when the supply voltage

is larger than the input voltage. Additionally, the 5V

tolerant input pins enable down translation when the

input voltage is larger than the supply voltage. The

output level is always referenced to the supply voltage

(VCC) and supports 1.8V, 2.5V, 3.3V, and 5V CMOS

levels.