SN74LV8T594-Q1中文资料德州仪器数据手册PDF规格书

1 Features

• AEC-Q100 qualified for automotive applications:

– Device temperature grade 1: -40°C to +125°C

– Device HBM ESD classification level 2

– Device CDM ESD classification level C4B

• Latching logic with known power-up state provides

consistent start-up behavior

• Wide operating range of 1.65 V to 5.5 V

• 5.5-V tolerant input pins

• Single-supply voltage translator (refer to LVxT

Enhanced Input Voltage):

– Up translation:

• 1.2 V to 1.8 V

• 1.5 V to 2.5 V

• 1.8 V to 3.3 V

• 3.3 V to 5.0 V

– Down translation:

• 5.0 V, 3.3 V, 2.5 V to 1.8 V

• 5.0 V, 3.3 V to 2.5 V

• 5.0 V to 3.3 V

• Up to 150Mbps with 5-V or 3.3-V VCC

• Supports standard function pinout

• Latch-up performance exceeds 250 mA

per JESD 17

2 Applications

• Digital signage

• Controlling an indicator LED

• Increase the number of outputs on a

microcontroller

3 Description

The SN74LV8T594-Q1 device contains an 8-bit,

serial-in, parallel-out shift register. Each parallel

output of the shift register is fed through a storage

register before reaching the primary device outputs

(QA through QH). Separate clocks (SRCLK and

RCLK) and direct overriding clear (SRCLR and

RCLR) inputs are provided for both the shift and

storage registers, allowing for loading data separately

from sending it to the outputs. Additionally, the last

output of the internal shift register is sent directly

to the output QH' providing a method to daisy-chain

multiple shift registers.

The input is designed with a reduced threshold circuit

to support up translation when the supply voltage

is larger than the input voltage. Additionally, the 5-

V tolerant input pins enable down translation when

the input voltage is larger than the supply voltage.

The output level is always referenced to the supply

voltage (VCC) and supports 1.8-V, 2.5-V, 3.3-V, and

5-V CMOS levels.