SN74LV126A数据手册集成电路（IC）的缓冲器驱动器接收器收发器规格书PDF

描述 Description

The ’LV126A quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

These quadruple bus buffer gates are designed for 2-V to 5.5-V VCC operation.

The ’LV126A devices feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

特性 Features

• 2-V to 5.5-V VCC Operation
• Max tpd of 6.5 ns at 5 V
• Typical VOLP (Output Ground Bounce) VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial Power Down Mode, and Back Drive Protection
• Support Mixed-Mode Voltage Operation on All Ports
• Latch-Up Performance Exceeds 250 mA per JESD 17
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)
• 1000-V Charged-Device Model (C101)