丝印：LV10A；Package：TSSOP；SN74LV10A Triple 3-Input Positive-NAND Gate

1 Features • VCC operation of 2 V to 5.5 V • Max tpd of 7 ns at 5 V • Typical VOLP (Output Ground Bounce) 2.3 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceed

文件：980.73 Kbytes 页数：22 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-NAND GATE

文件：332.68 Kbytes 页数：13 Pages

TI

德州仪器

TRIPLE 3-INPUT POSITIVE-NAND GATE

文件：474.83 Kbytes 页数：15 Pages

TI

德州仪器

Triple 3-input NAND gate

DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi

文件：113.24 Kbytes 页数：10 Pages

PHI

飞利浦

Triple 3-input NAND gate

DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi

文件：113.24 Kbytes 页数：10 Pages

PHI

飞利浦

Triple 3-input NAND gate

DESCRIPTION The 74LV10 is a low-voltage Si-gate CMOS device and is pin and function compatible with 74HC/HCT10. The 74LV10 provides the 3-input NAND function. FEATURES • Optimized for Low Voltage applications: 1.0 to 3.6 V • Accepts TTL input levels between VCC = 2.7 V and VCC = 3.6 V • Typi

文件：113.24 Kbytes 页数：10 Pages

PHI

飞利浦