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SN74LS243N

丝印:SN74LS243N;Package:PDIP;QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

文件:673.8 Kbytes 页数:18 Pages

TI

德州仪器

SN74LS243N.A

丝印:SN74LS243N;Package:PDIP;QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

文件:673.8 Kbytes 页数:18 Pages

TI

德州仪器

SN74LS243NE4

丝印:SN74LS243N;Package:PDIP;QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

文件:673.8 Kbytes 页数:18 Pages

TI

德州仪器

SN74LS243N

丝印:SN74LS243N;Package:PDIP;QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

文件:673.8 Kbytes 页数:18 Pages

TI

德州仪器

SN74LS243N.A

丝印:SN74LS243N;Package:PDIP;QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

文件:673.8 Kbytes 页数:18 Pages

TI

德州仪器

SN74LS243NE4

丝印:SN74LS243N;Package:PDIP;QUADRUPLE BUS TRANSCEIVERS

1FEATURES · Two-Way Asynchronous Communication Between Data Buses · PNP Inputs Reduce D-C Loading · Hysteresis (Typically 400 mV) at Inputs Improves Noise Margin DESCRIPTION These four-data-line transceivers are designed for asynchronous two-way communications between data buses. SN74LS2

文件:673.8 Kbytes 页数:18 Pages

TI

德州仪器

SN74LS243N

QUAD BUS TRANSCEIVER

The SN54/74LS242 and SN54/74LS243 are Quad Bus Transmitters/Receivers designed for 4-line asynchronous 2-way data communications between data buses. • Hysteresis at Inputs to Improve Noise Immunity • 2-Way Asynchronous Data Bus Communication • Input Clamp Diodes Limit High-Speed Termination Eff

文件:171.72 Kbytes 页数:5 Pages

Motorola

摩托罗拉

SN74LS243N

QUADRUPLE BUS TRANSCEIVERS

文件:135.01 Kbytes 页数:4 Pages

TI

德州仪器

SN74LS243N

QUADRUPLE BUS TRANSCEIVERS

文件:900.59 Kbytes 页数:14 Pages

TI

德州仪器

SN74LS243N3

QUADRUPLE BUS TRANSCEIVERS

文件:900.59 Kbytes 页数:14 Pages

TI

德州仪器

详细参数

  • 型号:

    SN74LS243N

  • 功能描述:

    总线收发器 Quad bus transceiver

  • RoHS:

  • 制造商:

    Fairchild Semiconductor

  • 逻辑类型:

    CMOS

  • 逻辑系列:

    74VCX

  • 每芯片的通道数量:

    16

  • 输入电平:

    CMOS

  • 输出电平:

    CMOS

  • 输出类型:

    3-State

  • 高电平输出电流:

    - 24 mA

  • 低电平输出电流:

    24 mA

  • 传播延迟时间:

    6.2 ns

  • 电源电压-最大:

    2.7 V, 3.6 V

  • 电源电压-最小:

    1.65 V, 2.3 V

  • 最大工作温度:

    + 85 C

  • 封装/箱体:

    TSSOP-48

  • 封装:

    Reel

供应商型号品牌批号封装库存备注价格
TI(德州仪器)
24+
PDIP14
924
只做原装,提供一站式配单服务,代工代料。BOM配单
询价
TEXAS
24+
DIP14P
6868
原装现货,可开13%税票
询价
TI
24+
DIP14
178
本站现库存
询价
MOT
25+
DIP-14P
4897
绝对原装!现货热卖!
询价
MOT
23+
40/DIP
5000
原装正品,假一罚十
询价
MOT
24+
DIP
6232
公司原厂原装现货假一罚十!特价出售!强势库存!
询价
MOTOROL
25+
DIP14
23
百分百原装正品 真实公司现货库存 本公司只做原装 可
询价
TI
24+/25+
65
原装正品现货库存价优
询价
TI
17+
DIP
6200
100%原装正品现货
询价
MOT
24+
DIP
3700
原装现货假一罚十
询价
更多SN74LS243N供应商 更新时间2025-9-21 8:11:00