9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

文件：75.18 Kbytes 页数：5 Pages

TI

德州仪器

9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

文件：299.76 Kbytes 页数：9 Pages

TI

德州仪器

9 位至 18 位 HSTL-To-LVTTL 存储器地址锁存器

This 9-bit to 18-bit D-type latch is designed for 3.15-V to 3.45-V VCC operation. The D inputs accept HSTL levels and the Q outputs provide LVTTL levels. The SN74HSTL16918 is particularly suitable for driving an address bus to two banks of memory. Each bank of nine outputs is controlled with its own • Member of the Texas Instruments WidebusTM Family• Inputs Meet JEDEC HSTL Std JESD 8-6 and Outputs Meet Level III Specifications• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)• Latch-Up Performance Exceeds 250 mA Per JESD 17• Packa;

TI

德州仪器

9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

文件：299.76 Kbytes 页数：9 Pages

TI

德州仪器

9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

文件：75.18 Kbytes 页数：5 Pages

TI

德州仪器

9-BIT TO 18-BIT HSTL-TO-LVTTL MEMORY ADDRESS LATCH

文件：299.76 Kbytes 页数：9 Pages

TI

德州仪器

Package：48-TFSOP（0.240"，6.10mm 宽）；包装：卷带（TR）剪切带（CT）Digi-Reel® 得捷定制卷带 类别：集成电路（IC） 锁存器 描述：IC MEMORY ADDRESS LATCH 48-TSSOP

TI2

德州仪器