DUAL J-K NEGATIVE-EDGE-TRIGGERED FLIP-FLOPS WITH PRESET, COMMON CLEAR, AND COMMON CLOCK

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TI

德州仪器

Dual J-K Flip-Flops (with Preset, Common Clear and Common Clock)

Description This flip-flop is edge sensitive to the clock input and change state on the negative transition of the clock pulse. each flip-flop has independent J, K and preset inputs and Q and Q outputs. Two flip-flops are controlled by a common clear and a common clock. Preset and clear are indep

文件：49 Kbytes 页数：8 Pages

HITACHIHitachi Semiconductor

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TI

德州仪器

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SOP14

TI/德州仪器

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SOIC-14

TI/德州仪器

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