QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

文件：459.76 Kbytes 页数：13 Pages

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德州仪器

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：66.22 Kbytes 页数：5 Pages

TI

德州仪器

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

文件：586.88 Kbytes 页数：12 Pages

TI

德州仪器

丝印：SN74F126N；Package：PDIP；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

文件：459.76 Kbytes 页数：13 Pages

TI

德州仪器

丝印：SN74F126N；Package：PDIP；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

文件：459.76 Kbytes 页数：13 Pages

TI

德州仪器

具有三态输出的 4 通道、4.5V 至 5.5V 双极缓冲器

The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low.\n\n To ensure the high-impedance state during power up or power down, OE should be tied to GND through a pulldown resistor; the minimum value o • 4.5-V to 5.5-V VC Operation\n• Max tpd of 6.5 ns at 5 V\n• 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers;

TI

德州仪器

丝印：F126；Package：SOIC；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

文件：459.76 Kbytes 页数：13 Pages

TI

德州仪器

丝印：F126；Package：SOIC；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

文件：459.76 Kbytes 页数：13 Pages

TI

德州仪器

丝印：F126；Package：SOIC；QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

文件：459.76 Kbytes 页数：13 Pages

TI

德州仪器

QUADRUPLE BUS BUFFER GATE WITH 3-STATE OUTPUTS

4.5-V to 5.5-V VCC Operation Max tpd of 6.5 ns at 5 V 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers description/ordering information The SN74F126 bus buffer features independent line drivers with 3-state outputs. Each output is disabled when the associated output-enab

文件：459.76 Kbytes 页数：13 Pages

TI

德州仪器