SN74AUP2G125中文资料具有三态输出的 2 通道、0.8V 至 3.6V 低功耗缓冲器数据手册TI规格书

描述 Description

The AUP family is TI’s premier solution to the industry’s low-power needs in battery-powered portable applications. This family ensures a very low static and dynamic power consumption across the entire VCC range of 0.8 V to 3.6 V, resulting in an increased battery life. This product also maintains excellent signal integrity (see Figure 1 and Figure 2). The SN74AUP2G125 is a dual bus buffer gate designed for 0.8-V to 3.6-V VCC operation. This device features dual line drivers with 3-state outputs. Each output is disabled when the corresponding output-enable (OE) input is high. This device has the input-disable feature, which allows floating input signals. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. NanoStar™ package technology is a major breakthrough in IC packaging concepts, using the die as the package. This device is fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the device when it is powered down.

特性 Features

• Available in the Texas Instruments NanoStar™ Package
• Low Dynamic-Power Consumption (Cpd = 4 pF Typ at 3.3 V)
• Low Noise – Overshoot and Undershoot CC
• Ioff Supports Partial-Power-Down Mode Operation
• Wide Operating VCC Range of 0.8 V to 3.6 V
• 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation
• Suitable for Point-to-Point Applications
• ESD Performance Tested Per JESD 22
• 1000-V Charged-Device Model (C101)

NanoStar is a trademark of Texas Instruments