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SN74ALVCH16901数据手册集成电路(IC)的通用总线功能规格书PDF

厂商型号 |
SN74ALVCH16901 |
参数属性 | SN74ALVCH16901 封装/外壳为64-TFSOP(0.240",6.10mm 宽);包装为管件;类别为集成电路(IC)的通用总线功能;产品描述:IC UNIV BUS TXRX 18BIT 64TSSOP |
功能描述 | 具有奇偶校验发生器/校验器的 18 位通用总线收发器 |
封装外壳 | 64-TFSOP(0.240",6.10mm 宽) |
制造商 | TI Texas Instruments |
中文名称 | 德州仪器 美国德州仪器公司 |
数据手册 | |
更新时间 | 2025-8-7 23:00:00 |
人工找货 | SN74ALVCH16901价格和库存,欢迎联系客服免费人工找货 |
SN74ALVCH16901规格书详情
描述 Description
This 18-bit (dual-octal) noninverting registered transceiver is designed for 1.65-V to 3.6-V VCC operation.
The SN74ALVCH16901 is a dual 9-bit to dual 9-bit parity transceiver with registers. The device can operate as a feed-through transceiver or it can generate/check parity from the two 8-bit data buses in either direction.
The SN74ALVCH16901 features independent clock (CLKAB or CLKBA), latch-enable (LEAB or LEBA), and dual 9-bit clock-enable (CLKENAB\\ or CLKENBA\\) inputs. It also provides parity-enable (SEL\\) and parity-select (ODD/EVEN\\) inputs and separate error-signal (ERRA\\ or ERRB\\) outputs for checking parity. The direction of data flow is controlled by OEAB\\ and OEBA\\. When SEL\\ is low, the parity functions are enabled. When SEL\\ is high, the parity functions are disabled and the device acts as an 18-bit registered transceiver.
To ensure the high-impedance state during power up or power down, OE\\ should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
The A and B I/Os and APAR and BPAR inputs have bus-hold circuitry. Active bus-hold circuitry holds unused or undriven data inputs at a valid logic state. Use of pullup or pulldown resistors with the bus-hold circuitry is not recommended.
特性 Features
• Member of the Texas Instruments Widebus+ Family
• UBT Transceiver Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Operates From 1.65 V to 3.6 V
• Max tpd of 4.4 ns at 3.3 V
• ±24-mA Output Drive at 3.3 V
• Simultaneously Generates and Checks Parity
• Option to Select Generate Parity and Check or Feed-Through Data/Parity in A-to-B or B-to-A Directions
• Bus Hold on Data Inputs Eliminates the Need for External Pullup/Pulldown Resistors
• Latch-Up Performance Exceeds 250 mA Per JESD 17
• ESD Protection Exceeds JESD 22
• 2000-V Human-Body Model (A114-A)
• 200-V Machine Model (A115-A)Widebus+ and UBT are trademarks of Texas Instruments Incorporated.
技术参数
- 制造商编号
:SN74ALVCH16901
- 生产厂家
:TI
- VCC(Min)(V)
:1.65
- VCC(Max)(V)
:3.6
- Channels(#)
:18
- IOL(Max)(mA)
:24
- IOH(Max)(mA)
:-24
- ICC(uA)
:40
- Input type
:Standard CMOS
- Output type
:3-State
- Features
:Balanced OutputsUltra high speed (tpd Positive input clamp diodeBus-hold
- Rating
:Catalog
- Operating temperature range(C)
:-40 to 85
- Package Group
:TSSOP | 64
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
TI/德州仪器 |
24+ |
NA/ |
4152 |
原厂直销,现货供应,账期支持! |
询价 | ||
TI/德州仪器 |
22+ |
TSSOP |
100000 |
代理渠道/只做原装/可含税 |
询价 | ||
TI |
24+/25+ |
863 |
原装正品现货库存价优 |
询价 | |||
LSSJ |
1736+ |
TSSOP64 |
8298 |
只做进口原装正品假一赔十! |
询价 | ||
TI |
23+ |
NA |
19854 |
专业电子元器件供应链正迈科技特价代理特价,原装元器件供应,支持开发样品 |
询价 | ||
SN74ALVCH16901DGGR |
1994 |
1994 |
询价 | ||||
TI |
23+ |
NA |
20000 |
询价 | |||
TI/德州仪器 |
2223+ |
TSSOP |
26800 |
只做原装正品假一赔十为客户做到零风险 |
询价 | ||
TI |
24+ |
TSSOP |
25000 |
一级专营品牌全新原装热卖 |
询价 | ||
MAXIM/美信 |
21+ |
TSSOP |
2856 |
百域芯优势 实单必成 可开13点增值税 |
询价 |