SN74ACT16

SN74ACT16 Hex Schmitt-Trigger Inverters with Open-Drain Outputs and TTLCompatible Inputs

1Features •Operatingvoltagerangeof4.5Vto5.5V •TTL-compatibleSchmitt-triggerinputssupportslow andnoisyinputsignals •Continuous24mAoutputdriveat5V •Supportsupto75mAoutputdriveat5V inshortbursts •Drives50Ωtransmissionlines •Fastoperationwithdelayof7.2

SN74ACT16

SN74ACT16 Hex Schmitt-Trigger Inverters with Open-Drain Outputs and TTLCompatible Inputs

1Features •Operatingvoltagerangeof4.5Vto5.5V •TTL-compatibleSchmitt-triggerinputssupportslow andnoisyinputsignals •Continuous24mAoutputdriveat5V •Supportsupto75mAoutputdriveat5V inshortbursts •Drives50Ωtransmissionlines •Fastoperationwithdelayof7.2

SN74ACT16

SN74ACT16 Hex Schmitt-Trigger Inverters with Open-Drain Outputs and TTLCompatible Inputs

1Features •Operatingvoltagerangeof4.5Vto5.5V •TTL-compatibleSchmitt-triggerinputssupportslow andnoisyinputsignals •Continuous24mAoutputdriveat5V •Supportsupto75mAoutputdriveat5V inshortbursts •Drives50Ωtransmissionlines •Fastoperationwithdelayof7.2

SN74ACT16

具有施密特触发 TTL 兼容型输入和开漏输出的 4.5V 至 5.5V 反相器; 4.5V 至 5.5V 的工作电压范围\n \nTTL 兼容型施密特触发输入支持慢速和高噪声输入信号\n \n电压为 5V 时，为 24mA 的连续输出驱动\n \n电压为 5V 时，支持高达 75mA 的输出驱动（短时突发）\n \n驱动 50Ω 传输线\n \n快速运行，延迟为 7.2ns（最大值）;

SN74ACT16 器件包含六个具有 TTL 兼容型施密特触发输入和开漏输出的独立 CMOS 逻辑反相器。

SN74ACT16245-EP

16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

ControlledBaseline –OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof –40°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProductChangeNotification QualificationPedigree† MemberoftheTexasInstruments WidebusFamily Inpu

SN74ACT16245QDLREP

16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

ControlledBaseline –OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof –40°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProductChangeNotification QualificationPedigree† MemberoftheTexasInstruments WidebusFamily Inpu

SN74ACT16245QDLREP.A

16-BIT BUS TRANSCEIVER WITH 3-STATE OUTPUTS

ControlledBaseline –OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof –40°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProductChangeNotification QualificationPedigree† MemberoftheTexasInstruments WidebusFamily Inpu

SN74ACT16373-EP

16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

ControlledBaseline –OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof –40°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProductChangeNotification QualificationPedigree† MemberoftheTexasInstruments WidebusFamily Inpu

SN74ACT16373-EP

具有施密特触发输入的增强型产品 16 通道、4.5V 至 5.5V 反相器; • Controlled Baseline \n• One Assembly/Test Site, One Fabrication Site\n \n• Extended Temperature Performance of –40°C to 125°C\n• Enhanced Diminishing Manufacturing Sources (DMS) Support\n• Enhanced Product Change Notification\n• Qualification Pedigree\n• Member of the Texas Instruments Widebus™ Family\n• Inputs Are TTL-Voltage Compatible\n• 3-State Bus Driving True Outputs\n• Full Parallel Access for Loading\n• Distributed VCC and GND Pins Minimize High-Speed Switching Noise\n Widebus is a trademark of Texas Instruments. Component qualification in accordance with JEDEC and industry standards to ensure reliable operation over an extended temperature range. This includes, but is not limited to, highly accelerated stress test (HAST) or biased 85/85, temperature cycle, autoclave or unbiased HAST, electromigration, bond intermetallic life, and mold compound life.;

The SN74ACT16373Q-EP is a 16-bit D-type transparent latch with 3-state outputs, designed specifically for driving highly capacitive or relatively low-impedance loads. It is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.\n\n This device can be used as two 8-bit latches or one 16-bit latch. The Q outputs of the latches follow the data (D) inputs if the latch-enable (LE) input is taken high. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.\n\n A buffered output-enable (OE)\\ input can be used to place the outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and the increased drive provide the capability to drive bus lines in a bus-organized system, without need for interface or pullup components.\n\n OE\\ does not affect the internal operations of the latches. Old data can be retained or new data can be entered while the outputs are in the high-impedance state.

SN74ACT16373QDLREP

16-BIT D-TYPE TRANSPARENT LATCH WITH 3-STATE OUTPUTS

ControlledBaseline –OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof –40°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProductChangeNotification QualificationPedigree† MemberoftheTexasInstruments WidebusFamily Inpu