SN74ACT10-Q1 Automotive Triple 3-Input Positive-NAND Gate

1 Features • Qualified for automotive applications • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Description The SN74ACT10 device contains three independent 3-input NAND gates. The device performs the Boolean

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德州仪器

SNx4ACT10 Triple 3-Input Positive-NAND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Alarm/tamper detect circuit • S-R latch 3 Description The SNx4ACT10 devices contain three independent 3-input NAND gates. The devices

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德州仪器

TRIPLE 3-INPUT POSITIVE-NAND GATES

文件：1.05287 Mbytes 页数：19 Pages

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TRIPLE 3-INPUT POSITIVE-NAND GATES

文件：79.9 Kbytes 页数：5 Pages

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德州仪器

TRIPLE-3-INPUT PSITIVE-NAND GATES

文件：692.08 Kbytes 页数：17 Pages

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丝印：SN74ACT10N；Package：PDIP(N)；SNx4ACT10 Triple 3-Input Positive-NAND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Alarm/tamper detect circuit • S-R latch 3 Description The SNx4ACT10 devices contain three independent 3-input NAND gates. The devices

文件：2.89914 Mbytes 页数：44 Pages

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德州仪器

丝印：SN74ACT10N；Package：PDIP(N)；SNx4ACT10 Triple 3-Input Positive-NAND Gates

1 Features • 4.5V to 5.5V VCC operation • Inputs accept voltages to 5.5V • Max tpd of 9.5ns at 5V • Inputs are TTL-voltage compatible 2 Applications • Alarm/tamper detect circuit • S-R latch 3 Description The SNx4ACT10 devices contain three independent 3-input NAND gates. The devices

文件：2.89914 Mbytes 页数：44 Pages

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德州仪器

具有 TTL 兼容型 CMOS 输入的 3 通道、3 输入、4.5V 至 5.5V 与非门

The ’ACT10 devices contain three independent 3-input NAND gates. The devices perform the Boolean functions Y = (A • B • C)\\ or Y = A\\ + B\\ + C\\ in positive logic. • 4.5-V to 5.5-V VCC Operation\n• Inputs Accept Voltages to 5.5 V\n• Max tpd of 9.5 ns at 5 V\n• Inputs Are TTL-Voltage Compatible;

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10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION

Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot Caused By Line Reflections Repetitive Peak Forward Current . . . IFRM = 100 mA Inputs Are TTL-Voltage Compatible Low Power Consumption (Like CMOS) ESD Protection Exceeds 2000 V

文件：355.7 Kbytes 页数：11 Pages

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丝印：ACT1071；Package：SOIC；10-BIT BUS-TERMINATION ARRAY WITH BUS-HOLD FUNCTION

Designed to Ensure Defined Voltage Levels on Floating Bus Lines in CMOS Systems Reduces Undershoot and Overshoot Caused By Line Reflections Repetitive Peak Forward Current . . . IFRM = 100 mA Inputs Are TTL-Voltage Compatible Low Power Consumption (Like CMOS) ESD Protection Exceeds 2000 V

文件：355.7 Kbytes 页数：11 Pages

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德州仪器