SN74ABT853DW.B中文资料德州仪器数据手册PDF规格书

State-of-the-Art EPIC-ΙΙB™ BiCMOS Design

Significantly Reduces Power Dissipation

ESD Protection Exceeds 2000 V Per

MIL-STD-883, Method 3015; Exceeds 200 V

Using Machine Model (C = 200 pF, R = 0)

Latch-Up Performance Exceeds 500 mA Per

JESD 17

Typical VOLP (Output Ground Bounce)

< 1 V at VCC = 5 V, TA = 25°C

High-Drive Outputs (−32-mA IOH, 64-mA IOL)

High-Impedance State During Power Up

and Power Down

Parity-Error Flag With Parity

Generator/Checker

Latch for Storage of Parity-Error Flag

Package Options Include Plastic

Small-Outline (DW), Shrink Small-Outline

DB), and Thin Shrink Small-Outline (PW)

Packages, Ceramic Chip Carriers (FK),

Ceramic Flat (W) Package, and Plastic (NT)

and Ceramic (JT) DIPs

description

The ’ABT853 8-bit to 9-bit parity transceivers are

designed for communication between data buses.

When data is transmitted from the A bus to the

B bus, a parity bit is generated. When data is

transmitted from the B bus to the A bus with its

corresponding parity bit, the open-collector

parity-error (ERR) output indicates whether or not

an error in the B data has occurred. The

output-enable (OEA and OEB) inputs can be used

to disable the device so that the buses are

effectively isolated. The ’ABT853 transceivers

provide true data at their outputs.

A 9-bit parity generator/checker generates a parity-odd (PARITY) output and monitors the parity of the I/O ports

with the ERR flag. The parity-error output can be passed, sampled, stored, or cleared from the latch using the

latch-enable (LE) and clear (CLR) control inputs. When both OEA and OEB are low, data is transferred from

the A bus to the B bus and inverted parity is generated. Inverted parity is a forced error condition that gives the

designer more system diagnostic capability.

When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down.

However, to ensure the high-impedance state above 2.1 V, OE should be tied to VCC through a pullup resistor;

the minimum value of the resistor is determined by the current-sinking capability of the driver.