SN74ABT162500中文资料具有三态输出的 18 位通用总线收发器数据手册TI规格书

描述 Description

These 18-bit universal bus transceivers combine D-type latches and D-type flip-flops to allow data flow in transparent, latched, and clocked modes. Data flow in each direction is controlled by output-enable (OEAB and OEBA\\), latch-enable (LEAB and LEBA), and clock (CLKAB\\ and CLKBA\\) inputs. For A-to-B data flow, the device operates in the transparent mode when LEAB is high. When LEAB is low, the A data is latched if CLKAB\\ is held at a high or low logic level. If LEAB is low, the A data is stored in the latch/flip-flop on the high-to-low transition of CLKAB\\. Output-enable OEAB is active high. When OEAB is high, the outputs are active. When OEAB is low, the outputs are in the high-impedance state.Data flow for B to A is similar to that of A to B but uses OEBA\\, LEBA, and CLKBA\\. The output enables are complementary (OEAB is active high and OEBA\\ is active low).The B-port outputs, which are designed to source or sink up to 12 mA, include equivalent 25- series resistors to reduce overshoot and undershoot.When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE\\ should be tied to VCC through a pullup resistor and OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sinking/current-sourcing capability of the driver. The SN54ABT162500 is characterized for operation over the full military temperature range of -55°C to 125°C. The SN74ABT162500 is characterized for operation from -40°C to 85°C. A-to-B data flow is shown: B-to-A flow is similar but uses OEBA\\, LEBA, and CLKBA\\. Output level before the indicated steady-state input conditions were established §Output level before the indicated steady-state input conditions were established, provided that CLKAB\\ was low before LEAB went low

特性 Features

• Members of the Texas InstrumentsWidebusTM Family
• B-Port Outputs Have Equivalent 25- Series Resistors, So No External Resistors Are Required
• State-of-the-ArtEPIC-II BTM BiCMOS Design Significantly Reduces Power Dissipation
• UBTTM (Universal Bus Transceiver) Combines D-Type Latches and D-Type Flip-Flops for Operation in Transparent, Latched, or Clocked Mode
• Typical VOLP (Output Ground Bounce) CC = 5 V, TA = 25°C
• High-Impedance State During Power Up and Power Down
• Flow-Through Architecture Optimizes PCB Layout
• Latch-Up Performance Exceeds 500 mAPer JESD 17
• ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0)
• Package Options Include Plastic Shrink Small-Outline (DL) Package and 380-mil Fine-Pitch Ceramic Flat (WD) Package Using 25-mil Center-to-Center Spacings Widebus, EPIC-IIB, and UBT are trademarks of Texas Instruments Incorporated.

简介

SN74ABT162500属于集成电路（IC）的通用总线功能。由TI制造生产的SN74ABT162500通用总线功能通用总线功能系列产品是元件级产品，用于处理或操作一系列（通常为 8 个或更多）并行逻辑信号（称为总线）。所执行的功能包括临时存储要发送或接收的数据，执行缓冲以允许输出电流容量有限的器件（例如微处理器）通过远距离互连高速传输数据，以及调换或移动总线内的位顺序等。