SN65LVDS94DGG.B中文资料德州仪器数据手册PDF规格书

FEATURES

· 4:28 Data Channel Expansion at up to 1.904

Gigabits per Second Throughput

· Suited for Point-to-Point Subsystem

Communication With Very Low EMI

· 4 Data Channels and Clock Low-Voltage

Differential Channels in and 28 Data and

Clock Out Low-Voltage TTL Channels Out

· Operates From a Single 3.3-V Supply and

250 mW (Typ)

· 5-V Tolerant SHTDN Input

· Rising Clock Edge Triggered Outputs

· Bus Pins Tolerate 4-kV HBM ESD

· Packaged in Thin Shrink Small-Outline

Package With 20 Mil Terminal Pitch

· Consumes <1 mW When Disabled

· Wide Phase-Lock Input Frequency Range

20 MHz to 68 MHz

· No External Components Required for PLL

· Meets or Exceeds the Requirements of ANSI

EIA/TIA-644 Standard

· Industrial Temperature Qualified

TA = -40°C to 85°C

· Replacement for the DS90CR286

DESCRIPTION

The SN65LVDS94 LVDS serdes (serializer/deserializer) receiver contains four serial-in 7-bit parallel-out shift

registers, a 7× clock synthesizer, and five low-voltage differential signaling (LVDS) line receivers in a single

integrated circuit. These functions allow receipt of synchronous data from a compatible transmitter, such as the

SN65LVDS93 and SN65LVDS95, over five balanced-pair conductors and expansion to 28 bits of single-ended

LVTTL synchronous data at a lower transfer rate.

When receiving, the high-speed LVDS data is received and loaded into registers at the rate seven times the

LVDS input clock (CLKIN). The data is then unloaded to a 28-bit wide LVTTL parallel bus at the CLKIN rate. A

phase-locked loop clock synthesizer circuit generates a 7× clock for internal clocking and an output clock for the

expanded data. The SN65LVDS94 presents valid data on the rising edge of the output clock (CLKOUT).