SN65LVDS117

双路 8 端口 LVDS 中继器; • Two Line Receivers and Eight ('109) or Sixteen ('117) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard\n• Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz\n• Outputs Arranged in Pairs From Each Bank\n• Enabling Logic Allows Individual Control of Each Driver Output Pair, Plus All Outputs\n• Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-Ω Load\n• Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks\n• Propagation Delay Times CC;

The SN65LVDS109 and SN65LVDS117 are configured as two identical banks, each bank having one differential line receiver connected to either four ('109) or eight ('117) differential line drivers. The outputs are arranged in pairs having one output from each of the two banks. Individual output enables are provided for each pair of outputs and an additional enable is provided for all outputs.\nThe line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)\nThe intended application of these devices, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 Ω. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock and data distribution trees.\nThe SN65LVDS109 and SN65LVDS117 are characterized for operation from –40°C to 85°C.\n \n

SN65LVDS117

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SN65LVDS117

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SN65LVDS117

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SN65LVDS117DGG

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SN65LVDS117DGG

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SN65LVDS117DGGG4

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SN65LVDS117DGGR

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SN65LVDS117DGGRG4

DUAL 4-PORT AND DUAL 8-PORT LVDS REPEATERS

SN65LVDS117DGGG4

Package：64-TFSOP（0.240"，6.10mm 宽）；包装：管件 类别：集成电路（IC） 信号缓冲器、中继器、分离器 描述：IC MULTIPLEXER 1CH 64TSSOP