SN65LVDS116中文资料1:16 LVDS 时钟扇出缓冲器数据手册TI规格书

特性 Features

• One Receiver and Sixteen Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard
• Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz
• Enabling Logic Allows Separate Control of Each Bank of Four Channels or 2-Bit Selection of Any One of the Four Banks
• Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100-. The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same substrate along with the low pulse skew of balanced signaling, allows extremely precise timing alignment of the signals repeated from the input. This is particularly advantageous in system clock distribution.The SN65LVDS116 is characterised for operation from –40°C to 85°C.