SN65LVDS108

1:8 LVDS 时钟扇出缓冲器; • One Line Receiver and Eight Line Drivers Configured as an 8-Port LVDS Repeater \n• Line Receiver and Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard\n• Typical Data Signaling Rates to 400 Mbps or Clock Frequencies to 400 MHz\n• Enabling Logic Allows Individual Control of Each Driver Output, Plus All Outputs\n• Low-Voltage Differential Signaling With Typical Output Voltage of 350 mV and a 100- Load\n• Electrically Compatible With LVDS, PECL, LVPECL, LVTTL, LVCMOS, GTL, BTL, CTT, SSTL, or HSTL Outputs With External Termination Networks\n• Propagation Delay Times CC;

The SN65LVDS108 is configured as one differential line receiver connected to eight differential line drivers. Individual output enables are provided for each output and an additional enable is provided for all outputs.\nThe line receivers and line drivers implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS, as specified in EIA/TIA-644, is a data signaling technique that offers low power, low noise emission, high noise immunity, and high switching speeds. (Note: The ultimate rate and distance of data transfer is dependent upon the attenuation characteristics of the media, the noise coupling to the environment, and other system characteristics.)\nThe intended application of this device, and the LVDS signaling technique, is for point-to-point or point-to-multipoint (distributed simplex) baseband data transmission on controlled impedance media of approximately 100 . The transmission media may be printed-circuit board traces, backplanes, or cables. The large number of drivers integrated into the same silicon substrate, along with the low pulse skew of balanced signaling, provides extremely precise timing alignment of the signals being repeated from the inputs. This is particularly advantageous for implementing system clock or data distribution trees.\nThe SN65LVDS108 is characterized for operation from –40°C to 85°C.\n\n

SN65LVDS108

4-PORT LVDS AND 4-PORT TTL-TO-LVDS REPEATERS

SN65LVDS108

8-PORT LVDS REPEATER

SN65LVDS108

8-PORT LVDS REPEATER

SN65LVDS108DBT

8-PORT LVDS REPEATER

FEATURES ·OneLineReceiverandEightLineDrivers Configuredasan8-PortLVDSRepeater ·LineReceiverandLineDriversMeetor ExceedtheRequirementsofANSIEIA/TIA-644 Standard ·TypicalDataSignalingRatesto400Mbpsor ClockFrequenciesto400MHz ·EnablingLogicAllowsIndivid

SN65LVDS108DBT.B

8-PORT LVDS REPEATER

FEATURES ·OneLineReceiverandEightLineDrivers Configuredasan8-PortLVDSRepeater ·LineReceiverandLineDriversMeetor ExceedtheRequirementsofANSIEIA/TIA-644 Standard ·TypicalDataSignalingRatesto400Mbpsor ClockFrequenciesto400MHz ·EnablingLogicAllowsIndivid

SN65LVDS108DBTG4

8-PORT LVDS REPEATER

FEATURES ·OneLineReceiverandEightLineDrivers Configuredasan8-PortLVDSRepeater ·LineReceiverandLineDriversMeetor ExceedtheRequirementsofANSIEIA/TIA-644 Standard ·TypicalDataSignalingRatesto400Mbpsor ClockFrequenciesto400MHz ·EnablingLogicAllowsIndivid

SN65LVDS108DBTR

8-PORT LVDS REPEATER

FEATURES ·OneLineReceiverandEightLineDrivers Configuredasan8-PortLVDSRepeater ·LineReceiverandLineDriversMeetor ExceedtheRequirementsofANSIEIA/TIA-644 Standard ·TypicalDataSignalingRatesto400Mbpsor ClockFrequenciesto400MHz ·EnablingLogicAllowsIndivid

SN65LVDS108DBTR.B

8-PORT LVDS REPEATER

FEATURES ·OneLineReceiverandEightLineDrivers Configuredasan8-PortLVDSRepeater ·LineReceiverandLineDriversMeetor ExceedtheRequirementsofANSIEIA/TIA-644 Standard ·TypicalDataSignalingRatesto400Mbpsor ClockFrequenciesto400MHz ·EnablingLogicAllowsIndivid

SN65LVDS108DBTRG4.B

8-PORT LVDS REPEATER

FEATURES ·OneLineReceiverandEightLineDrivers Configuredasan8-PortLVDSRepeater ·LineReceiverandLineDriversMeetor ExceedtheRequirementsofANSIEIA/TIA-644 Standard ·TypicalDataSignalingRatesto400Mbpsor ClockFrequenciesto400MHz ·EnablingLogicAllowsIndivid