SN54LS93数据手册TI中文资料规格书

描述 Description

Each of these monolithic counters contains four master-slave flip-flops and additional gating to provide a divide-by-two counter and a three-stage binary counter for which the count cycle length is divide-by-five for the '90A and 'LS90, divide-by-six for the '92A and 'LS92, and the divide-by eight for the '93A and 'LS93. All of these counters have a gated zero reset and the '90A and 'LS90 also have gated set-to-nine inputs for use in BCD nine's complement applications. To use their maximum count length (decade, divide-by-twelve, or four-bit binary) of these counters, the CKB input is connected to the QA output. The input count pulses are applied to CKA input and the outputs are as described in the appropriate function table. A symmetrical divide-by-ten count can be obtained from the '90A or 'LS90 counters by connecting the QD output to the CKA input and applying the input count to the CKB input which gives a divide-by-ten square wave at output QA.

特性 Features

• '90A, 'LS90 . . . Decade Counters
• '92A, 'LS92 . . . Divide By-Twelve Counters
• '93A, 'LS93 . . . 4-Bit Binary Counters
TYPES TYPICAL POWER DISSIPATION '90A 145 mW '92A, '93A 130 mW 'LS90, 'LS92, 'LS93 45 mW