SN54HC374-SP数据手册TI中文资料规格书

描述 Description

These 8-bit flip-flops feature 3-state outputs designed specifically for driving highly capacitive or relatively low-impedance loads. They are particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight flip-flops of the \\x92HC374 devices are edge-triggered D-type flip-flops. On the positive transition of the clock (CLK) input, the Q outputs are set to the logic levels that were set up at the data (D) inputs. An output-enable (OE) input places the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. The high-impedance state and increased drive provide the capability to drive bus lines without interface or pullup components. OE does not affect the internal operations of the flip-flops. Old data can be retained or new data can be entered while the outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.

特性 Features

• Wide Operating Voltage Range of 2 V to 6 V
• High-Current 3-State True Outputs Can Drive Up To 15 LSTTL Loads
• Eight D-Type Flip-Flops in a Single Package
• Full Parallel Access for Loading
• Low Power Consumption, 80-µA Max ICC
• Typical tpd = 14 ns
• ±6-mA Output Drive at 5 V
• Low Input Current of 1 µA Max