TRIPLE 3-INPUT POSITIVE-NAND GATES

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TI

德州仪器

TRIPLE 3-INPUT POSITIVE-NAND GATES

文件：76.9 Kbytes 页数：5 Pages

TI

德州仪器

具有清零和预置端的双路负边沿触发式 J-K 触发器

These devices contain two independent J-K\\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\\ or clear (CLR)\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\\ and CLR are inactive (high), data at the J and K\\ inputs meeting the setup-t • Wide Operating Voltage Range of 2 V to 6 V\n• Low Input Current of 1 µA Max\n• High-Current Outputs Drive Up To 10 LSTTL Loads\n• Low Power Consumption, 40-µA Max ICC\n• Typical tpd = 12 ns\n• ±4-mA Output Drive at 5 V;

TI

德州仪器

航天类 3 通道、3 输入、2V 至 6V 与非门

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y =  A ● B ● C in positive logic. • Buffered inputs\n• Wide operating voltage range: 2 V to 6 V\n• Wide operating temperature range: –40°C to +85°C\n• Supports fanout up to 10 LSTTL loads\n• Significant power reduction compared to LSTTL logic ICs;

TI

德州仪器