SN54HC10

TRIPLE 3-INPUT POSITIVE-NAND GATE

ControlledBaseline −OneAssembly/TestSite,OneFabrication Site ExtendedTemperaturePerformanceof −40°Cto125°C EnhancedDiminishingManufacturing Sources(DMS)Support EnhancedProduct-ChangeNotification QualificationPedigree† WideOperatingVoltageRangeof2Vto6V OutputsC

SN54HC10

SN74HC10-Q1 Automotive Triple 3-Input NAND Gates

1Features 1•AEC-Q100Qualifiedforautomotiveapplications: –Devicetemperaturegrade1: –40°Cto+125°C,TA •Bufferedinputs •Positiveandnegativeinputclampdiodes •Wideoperatingvoltagerange:2Vto6V •Supportsfanoutupto10LSTTLloads •Significantpowerreductioncompa

SN54HC10

军用 3 通道、3 输入、2V 至 6V 与非门; • Buffered inputs\n• Wide operating voltage range: 2 V to 6 V\n• Wide operating temperature range: –40°C to +85°C\n• Supports fanout up to 10 LSTTL loads\n• Significant power reduction compared to LSTTL logic ICs;

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y =  A ● B ● C in positive logic.

SN54HC10

TRIPLE 3-INPUT POSITIVE-NAND GATES

SN54HC10

TRIPLE 3-INPUT POSITIVE-NAND GATES

SN54HC10

TRIPLE 3-INPUT POSITIVE-NAND GATES

SN54HC109-SP

具有清零和预置端的双路负边沿触发式 J-K 触发器; • Wide Operating Voltage Range of 2 V to 6 V\n• Low Input Current of 1 µA Max\n• High-Current Outputs Drive Up To 10 LSTTL Loads\n• Low Power Consumption, 40-µA Max ICC\n• Typical tpd = 12 ns\n• ±4-mA Output Drive at 5 V;

These devices contain two independent J-K\\ positive-edge-triggered flip-flops. A low level at the preset (PRE)\\ or clear (CLR)\\ inputs sets or resets the outputs, regardless of the levels of the other inputs. When PRE\\ and CLR are inactive (high), data at the J and K\\ inputs meeting the setup-time requirements are transferred to the outputs on the positive-going edge of the clock (CLK) pulse. Clock triggering occurs at a voltage level and is not related directly to the rise time of the clock pulse. Following the hold-time interval, data at the J and K\\ inputs can be changed without affecting the levels at the outputs. These versatile flip-flops can perform as toggle flip-flops by grounding K\\ and tying J high. They also can perform as D-type flip-flops if J and K\\ are tied together.

SN54HC10-SP

航天类 3 通道、3 输入、2V 至 6V 与非门; • Buffered inputs\n• Wide operating voltage range: 2 V to 6 V\n• Wide operating temperature range: –40°C to +85°C\n• Supports fanout up to 10 LSTTL loads\n• Significant power reduction compared to LSTTL logic ICs;

This device contains three independent 3-input NAND gates. Each gate performs the Boolean function Y =  A ● B ● C in positive logic.

SN54HC10_07

TRIPLE 3-INPUT POSITIVE-NAND GATES

SN54HC10_15

TRIPLE 3-INPUT POSITIVE-NAND GATES