SM803中文资料12-Output Low Jitter Clock Generator数据手册Microchip规格书

描述 Description

The SM803xxx is a dual PLL clock generator that achieves ultra-low, 75fs RMS phase jitter. With 12 total outputs and dividers on each output, this device can generate 12 different frequencies up to 850MHz. It accepts a quartz crystal input or a reference clock input.Each output channel is individually configurable to LVPECL, LVDS, HCSL or LVCMOS output logic. For LVCMOS, only the true side of the channel is used. The SM803xxx is packaged in a dual row 84 pin 7mm x 7mm QFN package.



Create an application specific part and order samples with the CLOCKWORKS CONFIGURATOR tool.

特性 Features

• 75fs phase jitter @ 156.25MHz (1.875MHz to 20MHz)
• 180fs phase jitter @ 156.25MHz (12KHz to 20MHz)
• 2 high performance PLL synthesizers to generate multiple frequencies
• Independently programmable output logic and frequency
• Output logic: LVPECL, LVDS, HCSL, LVCMOS
• Crystal: 12MHz to 50MHz
• Reference Input: 12MHz to 850MHz
• No external crystal oscillator capacitors required
• 3.3V or 2.5V operating power supply
• Separate output power supplies
• Each bank can be at different levels (4 banks of 3 outputs each)
• Feedback input pins for use as zero delay buffer
• On chip power supply regulation for excellent power supply noise immunity
• Supports Commercial or Industrial temperature ranges
• Green, RoHS, and PFOS compliant
• Available in 48 pin, 84pin 7mm × 7mm and 76 pin 9mm x 9mm QFN package