SLG46811V集成电路（IC）的CPLD（复杂可编程逻辑器件）规格书PDF中文资料

 Multichannel Sampling Analog Comparator (MS ACMP)

 Sampling up to Four Analog Channels

 Selectable Voltage Reference for Each Channel

 Different Sampling Scenarios

 Synchronous or Asynchronous Result Appearance

 Integrated Voltage References (Vref)

 Twelve Combination Function Macrocells

 Two 2-Bit LUT or DFF/LATCH Macrocells

 One Selectable Programmable Pattern Generator or 2-bit LUT

 Four 3-Bit LUT or DFF/LATCH with Set/Reset

 Four Selectable DFF/LATCH or 3-bit LUTs or Shift Registers

 One 4-Bit LUT or DFF/LATCH with Set/Reset Macrocell

 Six Multi-Function Macrocells

 Five Selectable DFF/LATCH or 3-bit LUTs + 8-bit Delay/Counters

 One Selectable DFF/LATCH or 3-bit LUTs + 8-bit Delay/Counter/FSM

 Extended Pattern Generator

 Up to 8 Parallel Outputs

 92 bytes Pattern Stored in the NVM

 Serial Communications

 I2C Protocol Interface

 Programmable Delay with Edge Detector Output

 Deglitch Filter or Edge Detector