丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器

丝印：SCAN921226HSM；Package：NFBGA(NZA)；SCAN921025H and SCAN921226H High Temperature 20-80 MHz 10 Bit Bus LVDS SerDes with IEEE 1149.1 (JTAG) and at-speed BIST

1FEATURES 2• High Temperature Operation to 125°C • IEEE 1149.1 (JTAG) Compliant and At-Speed BIST Test Mode • Clock Recovery from PLL Lock to Random Data Patterns • Ensured Transition Every Data Transfer Cycle • Chipset (Tx + Rx) Power Consumption

文件：1.10383 Mbytes 页数：32 Pages

TI

德州仪器