SC18IS601数据手册恩XP中文资料规格书

描述 Description

General description
The SC18IS600/601 is designed to serve as an interface between the standard SPI of a host (microcontroller, microprocessor, chip set, etc.) and the serial I2C-bus. This allows the host to communicate directly with other I2C-bus devices. The SC18IS600/601 can operate as an I2C-bus master-transmitter or master-receiver. The SC18IS600/601 controls all the I2C-bus specific sequences, protocol, arbitration and timing.
The key distinction between the SC18IS600 and the SC18IS601 lies in the clock source: internal (SC18IS600) versus external (SC18IS601).

特性 Features

■ SPI slave interface
■ SPI Mode 3
■ Master I2C-bus controller
■ General Purpose Input/Output (GPIO) pins: 4 (SC18IS600); 3 (SC18IS601)
■ Two quasi-bidirectional I/O pins
■ 5 V tolerant I/O pins
■ High-speed SPI:
   ♦ Up to 3 Mbit/s (SC18IS601)
   ♦ Up to 1.2 Mbit/s (SC18IS600)
■ High-speed I2C-bus: 400 kbit/s
■ 96-byte transmit buffer
■ 96-byte receive buffer
■ 2.4 V to 3.6 V operation
■ Power-down mode with WAKEUP pin
■ Oscillator: internal (SC18IS600); external (SC18IS601)
■ Active LOW interrupt output
■ Available in very small TSSOP16 package