S3C24A0A中文资料PDF规格书
S3C24A0A规格书详情
ARCHITECTURAL OVERVIEW
The S3C24A0A is a 16/32-bit RISC microprocessor, designed to provide a cost-effective, low power, and high performance micro-controller solution for mobile phones and general applications. To provide a sufficient H/W performance for the 2.5G & 3G communication services, the S3C24A0A adopts dual-32-bit bus architecture and includes many powerful hardware accelerators for the motion video processing, serial communications, and etc. For the real time video conferencing, an optimized MPEG4 H/W Encoder/Decoder is integrated.
FEATURES
This section will explain the features of the S3C24A0A. Figure 1-1 is an overall block diagram of the S3C24A0A.
MICROPROCESSOR AND OVERALL ARCHITECTURE
• SoC (System-on-Chip) for mobile phones and general embedded applications.
• 16/32-Bit RISC architecture and powerful instruction set with ARM926EJ-S CPU core.
• ARM’s Jazelle Java technology enhanced ARM architecture MMU to support WinCE, Symbian and Linux
• Instruction cache, data cache, write buffer and Physical address TAG RAM to reduce the effect of main memory bandwidth and latency on performance
• 4 way set-associative cache with I-Cache (16KB) and D-Cache (16KB).
• 8-words per line with one valid bit and two dirty bits per line
• Pseudo random or round robin replacement algorithm.
• Write through or write back cache operation to update the main memory.
• The write buffer can hold 16 words of data and four addresses.
• ARM926EJ-S core supports the ARM debug architecture
• Internal AMBA (Advanced Microcontroller Bus Architecture) (AMBA2.0, AHB/APB)
• Dual AHB bus for high-performance processing (AHB-I & AHB-S)
MEMORY SUBSYSTEM
• High bandwidth Memory subsystem with two access channels (accesses from two AHB buses) and three-channel memory ports
• Double the bandwidth with the simultaneous access capability
• ROM/SRAM/NOR-Flash/NAND-Flash channel
• One SDRAM channels
• Up to 1GB Address space
• Low-power SDRAM interface support : Mobile SDRAM function
– DS: Driver Strength Control
– TCSR: Temperature Compensated Self-Refresh Control
– PASR: Partial Array Self-Refresh Control
• NAND Flash Boot Loader with the ECC circuitry to support booting from NAND Flash
– 4KB Stepping Stone
– Support 1G, 2G bit NAND Flash
产品属性
- 型号:
S3C24A0A
- 制造商:
SAMSUNG
- 制造商全称:
Samsung semiconductor
- 功能描述:
32-BIT RISC MICROPROCESSOR
供应商 | 型号 | 品牌 | 批号 | 封装 | 库存 | 备注 | 价格 |
---|---|---|---|---|---|---|---|
SAMSUNG/三星 |
21+ |
BGA |
11600 |
优势代理渠道,原装正品,可全系列订货开增值税票 |
询价 | ||
SAMSUNG/三星 |
2046+ |
9852 |
只做原装正品现货!或订货假一赔十! |
询价 | |||
SAMSUNG/三星 |
23+ |
NA/ |
3567 |
原厂直销,现货供应,账期支持! |
询价 | ||
SAMSUNG/三星 |
2019 |
BGA |
55000 |
专营原装正品现货 |
询价 | ||
SAMSUNG |
2023+ |
NEW |
80000 |
一级代理/分销渠道价格优势 十年芯程一路只做原装正品 |
询价 | ||
06/07+ |
QFP |
71 |
询价 | ||||
SAMSUNG |
BGA |
25 |
询价 | ||||
SAMSUNG/三星 |
19+ |
BGA |
16355 |
进口原装现货 |
询价 | ||
SAMSUNG |
23+ |
BGA |
8650 |
受权代理!全新原装现货特价热卖! |
询价 | ||
23+ |
N/A |
59210 |
正品授权货源可靠 |
询价 |